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| ? semiconductor components industries, llc, 2011 march, 2011 ? rev. 3 1 publication order number: ncp1015/d ncp1015 self-supplied monolithic switcher for low standby- power offline smps the ncp1015 integrates a fixed ? frequency current ? mode controller and a 700 v voltage mosfet. housed in a pdip ? 7 or sot ? 223 package, the ncp1015 offers everything needed to build a rugged and low ? cost power supply, including soft ? start, frequency jittering, short ? circuit protection, skip ? cycle, a maximum peak current set ? point and a dynamic self ? supply (no need for an auxiliary winding). unlike other monolithic solutions, the ncp1015 is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65 ? 100 khz). when the current set ? point falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so ? called skip cycle mode and provides excellent ef ficiency at light loads. because this occurs at typically 0.25 of the maximum peak value, no acoustic noise takes place. as a result, standby power is reduced to the minimum without acoustic noise generation. short ? circuit detection takes place when the feedback signal fades away e.g. un ? true short ? circuit or is broken optocoupler cases. finally soft ? start and frequency jittering further ease the designer task to quickly develop low ? cost and robust offline power supplies. for improved standby performance, the connection of an auxiliary winding stops the dss operation and helps to consume less than 100 mw at high line. features ? built ? in 700 v mosfet with typical r ds(on) of 11 ? large creepage distance between high ? voltage pins ? current ? mode fixed frequency operation: 65 khz ? 100 khz ? skip ? cycle operation at low peak currents only: no acoustic noise! ? dynamic self ? supply, no need for an auxiliary winding ? internal 1 ms soft ? start ? auto ? recovery internal output short ? circuit protection ? frequency jittering for better emi signature ? below 100 mw standby power if auxiliary winding is used ? internal temperature shutdown ? direct optocoupler connection ? spice models available for transient and ac analysis ? this is a pb ? free device typical applications ? low power ac ? dc adapters for chargers ? auxiliary power supplies (usb, appliances, tvs, etc.) pdip ? 7 case 626a ap suffix 1 8 marking diagrams p1015apyy awl yywwg 1 see detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. ordering information yy = 06 (65 khz), 10 (100 khz) y = a (65 khz), b (100 khz) a = assembly location wl = wafer lot yy = year ww = work week g or = pb ? free package http://onsemi.com pin connections 1 v cc 8 gnd 2 nc 3 gnd 4 fb 7 gnd 5 drain (top view) sot ? 223 case 318e st suffix 1 4 ayw 1015y 1 4 sot ? 223 (top view) 1 2 3 4 v cc fb drain gnd pdip ? 7 (*note: microdot may be in either location)
ncp1015 http://onsemi.com 2 indicative maximum output power from ncp1015 r ds(on) ? i p 230 vac 100 ? 250 vac 11 ? 450 ma dss 14 w 6.0 w 11 ? 450 ma auxiliary winding 19 w 8.0 w 1. informative values only, with: t amb = 50 c, circuit mounted on minimum copper area as recommended. figure 1. typical application example 27 3 45 18 100 ? 250 vac + + v out + gnd pin function description pin no. pin name function description sot ? 223 pdip ? 7 1 1 v cc powers the internal circuitry this pin is connected to an external capacitor of typically 10 f. the natural ripple superimposed on the v cc participates to the frequency jittering. for improved standby performance, an auxiliary v cc can be connected to pin 1. the v cc also includes an active shunt which serves as an opto fail ? safe protection. ? 2 nc ? ? ? 3 gnd the ic ground ? 2 4 fb feedback signal input by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 5 drain drain connection the internal drain mosfet connection. ? ? ? ? ? ? 7 gnd the ic ground ? 4 8 gnd the ic ground ? ncp1015 http://onsemi.com 3 65 khz 100 khz clock overload? uvlo management gnd nc v cc fb drain gnd gnd figure 2. simplified internal circuit architecture 2 1 3 4 4 v 18 k error flag armed? emi jittering v cc startup source drain flip ? flop d max = 65% reset reset high when v cc 3 v driver set q v cc 8 r sense 250 ns l.e.b. 7 5 ? + + - soft ? start startup sequence overload ? + 0.5 v drain maximum ratings symbol rating value unit v cc power supply voltage on all pins, except pin 5 (drain) ? 0.3 to 10 v vds drain voltage ? 0.3 to 700 v ids pk drain peak current during transformer saturation 1 a i_v cc maximum current into pin 1 15 ma r jl r ja r jl r ja thermal characteristics p suffix, case 626a junction ? to ? lead junction ? to ? air, 2.0 oz (70 m) printed circuit copper clad 0.36 sq. inch (2.32 sq. cm) 1.0 sq. inch (6.45 sq. cm) st suffix, plastic package case 318e junction ? to ? lead junction ? to ? air, 2.0 oz (70 m) printed circuit copper clad 0.36 sq. inch (2.32 sq. cm) 1.0 sq. inch (6.45 sq. cm) 9.0 77 60 14 74 55 c/w tj max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, human body model (hbm) (all pins except hv) 2 kv esd capability, machine model (mm) 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ncp1015 http://onsemi.com 4 electrical characteristics (for typical values t j =25 c, for min/max values t j = ? 40 cto125 c, v cc =8v unless otherwise noted) symbol rating pin min typ max unit supply section and v cc management v cc(off) v cc increasing level at which the current source turns ? off 1 7.9 8.5 9.1 v v cc(on) v cc decreasing level at which the current source turns ? on 1 6.9 7.5 8.1 v v cclatch decreasing level at which the latch ? off phase ends 1 4.4 4.7 5.1 v v cc hysteresis between v cc(off) 1 ? 1.0 ? icc1 internal ic consumption, mosfet switching at 65 khz 1 ? 0.92 1.1 ma icc1 internal ic consumption, mosfet switching at 100 khz 1 ? 0.95 1.15 ma v clamp active zener voltage positive offset to v cc(off) 1 140 200 300 mv power switch circuit r ds(on) power switch circuit on ? state resistance (id = 50 ma) t j = 25 c t j = 125 c 5 5 ? ? 11 ? 19 24 v dsb power switch circuit & startup breakdown voltage (i ds(off) = 100 a, t j = 25 c) 5 700 ? ? v i ds(off) power switch & startup breakdown voltage off ? state leakage current t j = ? 40 c (vds = 650 v) t j = 25 c (vds = 700 v) t j = 125 c (vds = 700 v) 5 5 5 ? ? ? 70 50 30 120 ? ? a t on t off switching characteristics (r l = 50 , vds set for ids = 0.7 x ids lim ) turn ? on time (90% ? 10%) turn ? off time (10% ? 90%) 5 5 ? ? 20 10 ? ? ns internal start ? up current source ic1 high ? voltage current source, v cc = 8 v 0 c < t j < 125 c ? 40 c < t j < 125 c 1 5.0 5.0 8.0 8.0 10 11 ma ic2 high ? voltage current source, v cc = 0 1 ? 10 ? ma current comparator t j = 25 c (note 2) i peak maximum internal current set ? point 5 405 450 495 ma i lskip default internal current set ? point for skip cycle operation, percentage ipeak max ? ? 25 ? % t del propagation delay from current detection to drain off state ? ? 125 ? ns t leb leading edge blanking duration ? ? 250 ? ns internal oscillator f osc oscillation frequency, 65 khz version, t j = 25 c (note 2) 59 65 71 khz f osc oscillation frequency, 100 khz version, t j = 25 c (note 2) 90 100 110 khz f dither frequency dithering compared to switching frequency (with active dss) ? 3.3 ? % d max maximum duty ? cycle 62 67 72 % feedback section r up internal pull ? up resistor 4 ? 18 ? k t ss internal soft ? start (guaranteed by design) ? ? 1.0 ? ms skip cycle generation v skip default skip mode level on fb pin 4 0.5 v temperature management tsd temperature shutdown 150 c hysteresis in shutdown 50 c 2. see characterization curves for temperature evolution ncp1015 http://onsemi.com 5 typical characteristics figure 3. ic1 @ v cc = 8.0 v, fb = 1.5 v vs. temperature ? 12 ? 9 ? 8 ? 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 20 0 20 40 60 100 120 temperature ( c) ic1 ( ma) figure 4. icc1 @ v cc = 8.0 v, fb = 1.5 v vs. temperature 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 ? 20 0 20 40 60 100 120 temperature ( c) icc1 (ma) figure 5. icc2 @ v cc = 6.0 v, fb = open vs. temperature 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40 ? 40 0 20 40 60 80 120 temperature ( c) icc2 (ma) figure 6. v cc off, fb = 1.5 v vs. temperature 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.0 ? 40 0 20 40 60 100 120 temperature ( c) vcc ? off ( v ) ? 40 80 ? 10 ? 11 ? 40 80 ? 20 100 ? 20 80 ncp1015 http://onsemi.com 6 typical characteristics figure 7. v cc on, fb = 3.5 v vs. temperature 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8.0 ? 20 0 20 40 60 100 120 temperature ( c) vcc ? on ( v) figure 8. duty cycle vs. temperature 66 67 68 69 ? 40 0 20 40 60 100 120 temperature ( c) duty cycle (%) ? 40 80 80 ? 20 figure 9. ipeak ? rr, v cc = 8.0 v, fb = 3.5 v vs. temperature 350 400 450 500 550 600 ? 40 0 20 40 60 100 120 temperature ( c) ipeak (ma) figure 10. frequency vs. temperature 50 60 70 80 90 100 110 ? 20 0 20 40 60 100 120 temperature ( c) 100 khz 65 khz figure 11. on resistance vs. temperature 0 5 10 15 20 25 ? 40 0 20 40 80 100 120 temperature ( c) r dson ( ) f osc (khz) ? 20 80 ? 40 80 60 ? 20 ncp1015 http://onsemi.com 7 application information introduction the ncp1015 offers a complete current ? mode control solution (actually an enhanced ncp1200 controller section) together with a high ? voltage power mosfet in a monolithic structure. the component integrates everything needed to build a rugged and low ? cost switch ? mode power supply (smps) featuring low standby power. the quick selection table details the differences in operating frequency. ? no need for an auxiliary winding: on semiconductor very high voltage integrated circuit technology lets you supply the ic directly from the high ? voltage dc rail. we call it dynamic self ? supply (dss). this solution simplifies the transformer design and ensures a better control of the smps in difficult output conditions, e.g. constant current operations. however, for improved standby performance, an auxiliary winding can be connected to the v cc pin to disable the dss operation. ? short ? circuit protection: by permanently monitoring the feedback line activity, the ic is able to detect the presence short ? circuit, immediately reducing the output power for a total system protection. once the short has disappeared, the controller resumes and goes back to normal operation. ? low standby ? power: if smps naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping un ? needed switching cycles, the ncp1015 drastically reduces the power wasted during light load conditions. an auxiliary winding can further help decreasing the standby power to extremely low levels by invalidating the dss operation. typical measurements show results below 80 mw @ 230 vac for a typical 7 w universal power supply. ? no acoustic noise while operating: instead of skipping cycles at high peak currents, the ncp1015 waits until the peak current demand falls below a fixed 0.25 of the maximum limit. as a result, cycle skipping can take place without having a singing transformer. you can thus select cheap magnetic components free of noise problems. ? spice model: a dedicated model to run transient cycle ? by ? cycle simulations is available but also an averaged version to help you closing the loop. ready ? to ? use templates can be downloaded in orcad?s pspice, and intusoft?s isspice4 from on semiconductor web site, ncp1015 related section. dynamic self ? supply when the power supply is first powered from the mains outlet, the internal current source (typically 8 ma) is biased and charges up the v cc capacitor from the drain pin. once the voltage on this v cc capacitor reaches the v cc(off) level (typically 8.5 v), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power mosfet. figure 12 details the internal circuitry: figure 12. the current source regulates v cc by introducing a ripple vref off = 8.5 v vref on = 7.5 v vref latch = 4.7 v - + internal supply + vref v cc(off) +200 mv (8.7 v typ.) v cc + cv cc startup source drain being loaded by the circuit consumption, the voltage on the v cc capacitor goes down. when the dss controller detects that v cc has reached 7.5 v (v cc(on) ), it activates the internal current source to bring v cc toward 8.5 v and stops again: a cycle takes place whose low frequency depends on the v cc capacitor and the ic consumption. a 1 v ripple takes place on the v cc pin whose average value equals (v cc(off) + v cc(on) ) / 2. figure 13 shows a typical operation of the dss. ncp1015 http://onsemi.com 8 0 2.00 4.00 6.00 8.00 startup period vcc 8.5v 7.5v device internally pulses figure 13. the charge/discharge cycle over a 10 f v cc capacitor as one can see, the v cc capacitor shall be dimensioned to offer an adequate startup time, i.e. ensure regulation is reached before v cc crosses 7.5 v (otherwise the part enters the fault condition mode). if we know that v = 1 v and icc1 is 1.2 ma (for instance we selected a 11 device switching at 65 khz), then the v cc capacitor can be calculated using: c icc1 t startup v (eq. 1) let?s suppose that the smps needs 10 ms to startup, then we will calculate c to offer a 15 ms period. as a result, c should be greater than 18 f thus the selection of a 33 f / 16 v capacitor is appropriate. short circuit protection the internal protection circuitry involves a patented arrangement that permanently monitors the assertion of an internal error flag. this error flag is, in fact, a signal that instructs the controller that the internal maximum peak current limit is reached. this naturally occurs during the startup period (v out is not stabilized to the target value) or when the optocoupler led is no longer biased, e.g in a short ? circuit condition or when the feedback network is broken. when the dss normally operates, the logic checks for the presence of the error flag every time v cc crosses v cc(on) . if the error flag is low (peak limit not active) then the ic works normally. if the error signal is active, then the ncp1015 immediately stops the output pulses, reduces its internal current consumption and does not allow the startup source to activate: v cc drops toward ground until it reaches the so ? called latch ? off level, where the current source activates again to attempt a new re ? start. if the error has gone, the ic automatically resumes its operation. if the default is still there, the ic pulses during 8.5 v down to 7.5 v and enters a new latch ? off phase. the resulting burst operation guarantees a low average power dissipation and lets the smps sustain a permanent short ? circuit. figure 14 presents the corresponding diagram: figure 14. simplified ncp1015 short ? circuit detection circuitry ? + 4 v fb division max ip flag v cc v cc(on) to latch reset current sense information clamp active? the protection burst duty ? cycle can easily be computed through the various timing events as portrayed by figure 15: ncp1015 http://onsemi.com 9 figure 15. ncp1015 facing a fault condition (v in = 150 vdc) tstart ts w tlatch 1 v ripple latch ? off level the rising slope from the latch ? off level up to 8.5 v is expressed by: p dss v in icc1 t start v1 c ic1 the time during which the ic actually pulses is given by: t sw v2 c icc1 finally, the latch ? off time can be derived using the same formula topology: t latch v3 c icc2 from these three definitions, the burst duty ? cycle d can be computed: d t sw t start t sw t latch (eq. 2) d v2 icc1 v2 icc1 v1 ic1 v3 icc2 (eq. 3) feeding the equation with values extracted from the parameter section gives a typical duty ? cycle d of 13%, precluding any lethal thermal runaway while in a fault condition. dss internal dissipation the dynamic self ? supplied pulls the energy out from the drain pin. in the flyback ? based converters, this drain level can easily go above 600 v peak and thus increase the stress on the dss startup source. however, the drain voltage evolves with time and its period is small compared to that of the dss. as a result, the averaged dissipation, excluding capacitive losses, can be derived by: p dss icc1 v ds(t) (eq. 4) figure 16 shows a typical drain ? ground wave ? shape where leakage effects have been removed: figure 16. a typical drain ? ground waveshape where leakage effects are not accounted for vds(t) vin vr toff dt ton t ts w by looking at figure 16 the average result can easily be derived by additive square area calculation: v ds(t) v in (1 d) v r t off t sw (eq. 5) by developing equation 5 we obtain: v ds(t) v in v in t on t sw v r t off t sw (eq. 6) t off can be expressed by: t off i p l p v r (eq. 7) t on can be evaluated by: t on i p l p v in (eq. 8) ncp1015 http://onsemi.com 10 plugging equation 7 and equation 8 into equation 6 leads to v clamp i trip r lim v stby v cc(on) icc1 (eq. 10) where: v nom is the auxiliary voltage at nominal load v stdby is the auxiliary voltage when standby is entered i trip is the current corresponding to the nominal operation. it thus must be selected to avoid false tripping in overshoot conditions. icc1 is the controller consumption. this number slightly decreases compared to icc1 from the spec since the part in standby does almost not switch. v cc(on) is the level above which v aux must be maintained to keep the dss in the off mode. it is good to shoot around 8 v in order to offer an adequate design margin, e.g. to not re ? activate the startup source (which is not a problem in itself if low standby power does not matter) since r limit shall not bother the controller in standby, e.g. keep v aux to around 8 v (as selected above), we purposely select a v nom well above this value. as explained before, experience shows that a 40% decrease can be seen on auxiliary windings from nominal operation down to standby mode. let?s select a nominal auxiliary winding of 20 v to offer sufficient margin regarding 8 v when in standby (r limit also drops voltage in standby). plugging the values in equation 10 gives the limits within which r limit shall be selected: 20 8.7 6.3 m r limit 12 8 1.1 m (eq. 11) that is to say: 1.8 k < r limit < 3.6 k . if we are designing a power supply delivering 12 v, then the ratio auxiliary/power must be: 12 / 20 = 0.6. the i cc current has to not exceed 6.4 ma. this will occur when v aux grows ? up to: 8.7 v + 1.8 k x (6.4 m + 1.1 m) = 22.2 v for the first boundary or 8.7 v + 3.6 k x (6.4 m +1.1 m) = 35.7 v for second boundary. on the power output, it will respectively give 22.6 x 0.6 = 13.3 v and 35.7 x 0.6 = 21.4 v. as one can see, tweaking the r limit value will allow the selection of a given overvoltage output level. theoretically predicting the auxiliary drop from nominal to standby is an almost impossible exercise since many parameters are involved, including the converter time constants. fine tuning of r limit thus requires a few iterations and experiments on a breadboard to check v aux variations but also output voltage excursion in fault. once properly adjusted, the fail ? safe protection will preclude any lethal voltage runaways in case a problem would occur in the feedback loop. ncp1015 http://onsemi.com 11 figure 17. a detailed view of the ncp1015 with properly connected auxiliary winding startup source drain + - ? + v cc(off) = 8.5 v v cc(on) = 7.5 v + v cc rlimit + + cvcc caux laux ground + d1 figure 18. the burst frequency becomes so low that it is difficult to keep an adequate level on the auxiliary v cc 30 ms lowering the standby power with skip ? cycle skip cycle offers an efficient way to reduce the standby power by skipping unwanted cycles at light loads. however, the recurrent frequency in skip often enters the audible range and a high peak current obviously generates acoustic noise in the transformer. the noise takes its origins in the resonance of the transformer mechanical structure which is excited by the skipping pulses. a possible solution, successfully implemented in the ncp1200 series, also authorizes skip cycle but only when the power demand as dropped below a given level. at this time, the peak current is reduced and no noise can be heard. figure 19 shows the peak current evolution of the ncp1015 entering standby: ncp1015 http://onsemi.com 12 figure 19. low peak current skip ? cycle guarantees noise ? free operation 100% peak current at nominal power 25% skip ? cycle current limit full power operation involves the nominal switching frequency and thus avoids any noise when running. experiments carried on a 5 w universal mains board unveiled a standby power of 300 mw @ 230 vac with the dss activated and dropped to less than 100 mw when an auxiliary winding is connected. frequency jittering for improved emi signature by sweeping the switching frequency around its nominal value, it spreads the energy content on adjacent frequencies rather than keeping it centered in one single ray. this of fers the benefit to artificially reduce the measurement noise on a standard emi receiver and pass the tests more easily. the emi sweep is implemented by routing the v cc ripple (induced by the dss activity) to the internal oscillator. as a result, the switching frequency moves up and down to the dss rhythm. typical deviation is 4% of the nominal frequency. with a 1 v peak ? to ? peak ripple, the frequency will equal 65 khz in the middle of the ripple and will increase as v cc rises or decrease as v cc ramps down. figure 20 shows the behavior we have adopted: figure 20. the v cc ripple causes the frequency jittering on the internal oscillator saw ? tooth (65 khz version) v cc ripple vcc off 67.6 khz 65 khz 62.4 khz vcc on internal sawtooth ncp1015 http://onsemi.com 13 soft ? start the ncp1015 features an internal 1 ms soft ? start activated during the power on sequence (p on ). as soon as v cc reaches v cc(off) , the peak current is gradually increased from nearly zero up to the maximum internal clamping level (e.g. 350 ma). this situation lasts 1 ms and further to that time period, the peak current limit is blocked to the maximum until the supply enters regulation. the soft ? start is also activated during the over current burst (ocp) sequence. every re ? start attempt is followed by a soft ? start activation. generally speaking, the soft ? start will be activated when v cc ramps up either from zero (fresh power ? on sequence) or 4.5 v, the latch ? off voltage occurring during ocp. figure 21 shows the soft ? start behavior. the time scales are purposely shifted to offer a better zoom portion. figure 21. soft ? start is activated during a start ? up sequence or an ocp condition 0 v (fresh pon) or 4.7 v (overload) v cc 8.5 v current sense max ip 1.0 ms non ? latching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its re ? start once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the internal skip level (v skip ), the output pulses are disabled. as soon as fb is relaxed, the ic resumes its operation. figure 22 shows the application example: figure 22. a non ? latching shutdown where pulses are stopped as long as the npn is biased on/off 27 3 45 18 transformer + cv cc full latching shutdown other applications require a full latching shutdown, e.g. when an abnormal situation is detected (over temp or overvoltage). this feature can easily be implemented through two external transistors wired as a discrete scr. when the ovp level exceeds the zener breakdown voltage, the npn biases the pnp and fires the equivalent scr, permanently bringing down the fb pin. the switching pulses are disabled until the user un ? plugs the power supply. ncp1015 http://onsemi.com 14 figure 23. two bipolar transistors ensures a total latch ? off of the smps in presence of an ovp 27 3 45 18 transformer + cv cc bat54 10 k 10 k ovp rhold 12 k 0.1 f r hold ensures that the scr stays on when fired. the bias current flowing through r hold should be small enough to let the v cc ramp up (8.5 v) and down (7.5 v) when the scr is fired. the npn base can also receive a signal from a temperature sensor. typical bipolar can be mmbt2222 and mmbt2907 for the discrete latch. the nst3946 features two bipolar npn + pnp in the same package and could also be used. power dissipation and heatsinking the power dissipation of ncp1015 consists of the dissipation dss current ? source (when active) and the dissipation of mosfet. thus p tot = p dss + p mosfet . when the pdip7 package is surrounded by copper, it becomes possible to drop its thermal resistance junction ? to ? ambient, r ja down to 75 c/w and thus dissipate more power. the maximum power the device can thus evacuate is: p max t j(max) t amb(max) r ja (eq. 12) which gives around 1 w for an ambient of 50 c. the losses inherent to the mosfet r ds(on) can be evaluated using the following formula: p mos 1 3 i p 2 d r ds(on) (eq. 13) where i p is the worse case peak current (at the lowest line input), d is the converter operating duty ? cycle and r ds(on) the mosfet resistance for t j = 100 c. this formula is only valid for discontinuous conduction mode (dcm) operation where the turn ? on losses are null (the primary current is zero when you re ? start the mosfet). figure 24 gives a possible layout to help dropping the thermal resistance. when measured on a 35 m (1 oz.) copper thickness pcb, we obtained a thermal resistance of 75 c/w: figure 24. a possible pcb arrangement to reduce the thermal resistance junction ? to ? ambient clamping elements dc to secondary diode design procedure the design of a smps around a monolithic device does not differ from that of a standard circuit using a controller and a mosfet. however, one needs to be aware of certain characteristics specific of monolithic devices: 1. in any case, the lateral mosfet body ? diode shall never be forward biased, either during start ? up (because of a large leakage inductance) or in normal operation as shown by figure 25. ncp1015 http://onsemi.com 15 figure 25. the drain ? source wave shall always be positive . . . 1.004m 1.011m 1.018m 1.025m 1.032m ? 50.0 50.0 150 250 350 > 0 !! as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: n (v out v f ) v in(min) (eq. 14) for instance, if you operate from a 120 v dc rail and you deliver 12 v, we can select a reflected voltage of 100 vdc maximum: 120 ? 100 > 0. therefore, the turn ratio np : ns must be smaller than 100 / (12 + 1) = 7.7 or np : ns < 7.7. we will see later on how it affects the calculation. 2. current ? mode architecture is, by definition, sensitive to subharmonic oscillations. subharmonic oscillations only occur when the smps is operating in continuous conduction mode (ccm) together with a duty ? cycle greater than 50%. as a result, we recommend operating the device in dcm only, whatever duty ? cycle it implies (max. = 65%). 3. lateral mosfets have a poorly doped body ? diode which naturally limits their ability to sustain the avalanche. a traditional rcd clamping network shall thus be installed to protect the mosfet. in some low power applications, a simple capacitor can also be used since: v drain(max) v in n (v out v f ) i p l f c tot (eq. 15) where l f is the leakage inductance, c tot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), n the np : ns turn ratio, v out the output voltage, v f the secondary diode forward drop and finally, i p the maximum peak current. worse case occurs when the smps is very close to regulation, e.g. the v out target is almost reached and i p is still pushed to the maximum. taking into account all previous remarks, it becomes possible to calculate the maximum power that can be transferred at low line: when the switch closes, v in is applied across the primary inductance l p until the current reaches the level imposed by the feedback loop. the duration of this event is called the on time and can be defined by: t on l p i p v in (eq. 16) at the switch opening, the primary energy is transferred to the secondary and the flyback voltage appears across l p , reseting the transformer core with a slope of: n (v out v f ) l p t off the t off time is thus: t off l p i p n (v out v f ) (eq. 17) if one wants to keep dcm only, but still need to pass the maximum power, we will not allow a dead ? time after the core is reset, but rather immediately re ? start. the switching time t sw can be expressed by: t sw t off t on l p i p 1 v in 1 n (v out v f ) (eq. 18) the flyback transfer formula dictates that: p out 1 2 l p i p 2 f sw (eq. 19) which, by extracting i p and plugging into equation 19 leads to: t sw l p 2 p out f sw l p 1 v in 1 n (v out v f ) (eq. 20) extracting l p from equation 20 gives: ncp1015 http://onsemi.com 16 l pcritical (v in v r ) 2 2 f sw [p out (v r 2 2 v r v in v in 2 )] (eq. 21) with v r = n . (v out + v f ) and the efficiency. if l p critical gives the inductance value above which dcm operation is lost, there is another expression we can write to connect l p , the primary peak current bounded by the ncp1015 and the maximum duty ? cycle that needs to stay below 50%: l p(max) d max v in(min) t sw i p(max) (eq. 22) where v in(min) corresponds to the lowest bulk voltage, hence the longest ton duration or largest duty ? cycle. i p(max) is the available peak current from the considered part, e.g. 450 ma typical for the ncp1015 (however, the minimum value of this parameter shall be considered for reliable evaluation). combining equations 21 and 22 gives the maximum theoretical power you can pass respecting the peak current capability of the ncp1015, the maximum duty ? cycle and the discontinuous mode operation: p max t sw 2 v in(min) 2 v r 2 f sw (2l p(max) v r 2 4l p(max) v r v in(min) v in(min) 2 ) (eq. 23) from equation 22 we obtain the operating duty ? cycle d: d i p l p v in t sw (eq. 24) this lets us calculate the rms current circulating in the mosfet: i d(rms) i p d 3 (eq. 25) from this equation, we obtain the average dissipation in the mosfet: p avg 1 3 i p 2 d r ds(on) (eq. 26) to which switching losses shall be added. if we stick to equation 23, compute lp and follow the above calculations, we will discover that a power supply built with the ncp1015 and operating from a 100 vac line minimum will not be able to deliver more than 7 w continuous, regardless of the selected switching frequency (however the transformer core size will go down as f sw is increased). this number grows up significantly when operated from single european mains (18 w). for more different flyback converters then are the below examples we recommend use following support: 1) application note and8125/d ?evaluating the power capability of the ncp101x members? 2) application note and8134/d ?designing converters with the ncp101x members.? 3) application note and8142/d ?a 6w/12w universal mains adapter with ncp101x series?. 4) the pspice or orcad simulation models example 1.: a 12 v 7.0 w smps operating on a large mains with ncp1015: v in = 100 vac 250 vac or 140 vdc 350 vdc once rectified, assuming a low bulk ripple efficiency = 80% v out = 12 v, i out = 580 ma f sw = 65 khz i p(max) = 450 ma ? 10% = 405 ma applying the above equations leads to : selected maximum reflected voltage = 120 v with v out = 12 v, secondary drop = 0.5 v np : ns = 1 : 0.1 l p critical = 3.9 mh i p = 250 ma d max = 0.39 i drain(rms) = 90 ma p mosfet = 202 mw at r ds(on) = 25 (t j > 100 c) p dss = 1.2 ma x 350 v = 420 mw, if dss is used secondary diode voltage stress = (350 x 0.1) + 12 = 47 v (e.g. a mbrs360t3, 3 a / 60 v would fit) example 2.: a 12 v 16 w smps operating on narrow european mains with ncp1015: v in = 230 vac 15%, or 276 vdc 370 vdc efficiency = 80% v out = 12 v, i out = 1.25 a f sw = 65 khz i p(max) = 450 ma ? 10% = 405 ma applying the equations leads to : selected maximum reflected voltage = 250 v with v out = 12 v, secondary drop = 0.5 v np : ns = 1:0.05 l p = 7,2 mh i p = 0.27 ma d max = 0.41 i drain(rms) = 100 ma p mosfet = 250 mw at r ds(on) = 25 (t j > 100 c) p dss = 1.2 ma x 370 v = 444 mw, if dss is used below an ambient of 50 c. secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 v (e.g. a mbrs340t3, 3 a / 40 v) ncp1015 http://onsemi.com 17 please note that these calculations assume a flat dc rail whereas a 10 ms ripple naturally affects the final voltage available on the transformer end. once the bulk capacitor has been selected, one should check that the resulting ripple (min v bulk ?) is still compatible with the above calculations. as an example, to benefit from the largest operating range, a 7 w board was built with a 47 f bulk capacitor which ensured discontinuous operation even in the ripple minimum waves. mosfet protection as in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the mosfet bvdss which is 700 v. figures 26a, b, and c present possible implementations: figure 26. different options to clamp the leakage spike 1 2 3 45 8 6 7 cvcc hv cclamp rclamp d 1 2 3 45 8 6 7 ncp1015 cvcc hv c 1 2 3 45 8 6 7 ncp1015 cvc c d hv dz a c b ncp1015 figure 26a: the simple capacitor limits the voltage according to equation 15. this option is only valid for low power applications, e.g. below 5 w, otherwise chances exist to destroy the mosfet. after evaluating the leakage inductance, you can compute c with equation 15. typical values are between 100 pf and up to 470 pf. large capacitors increase capacitive losses. figure 26b: the most standard circuitry called the rcd network. you calculate r clamp and c clamp using the following formulas: r clamp 2 v clamp (v clamp (v out v f sec) n) l leak i p 2 f sw (eq. 27) c clamp v clamp v ripple f sw r clamp (eq. 28) v clamp is usually selected 50 ? 80 v above the reflected value n x (v out + v f ). the diode needs to be a fast one and a mur160 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. worse case occurs when i p and v in are maximum and v out is close to reach the steady ? state value. figure 26c: this option is probably the most expensive of all three but it offers the best protection degree. if you need a very precise clamping level, you must implement a zener diode or a tvs. there are little technology differences behind a standard zener diode and a tvs. however, the die area is far bigger for a transient suppressor than that of zener. a 5 w zener diode like the 1n5388b will accept 180 w peak power if it lasts less than 8.3 ms. if the peak current in the worse case (e.g. when the pwm circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 w, then the diode will be destroyed when the supply experiences overloads. a transient suppressor like the p6ke200 still dissipates 5 w of continuous power but is able to accept surges up to 600 w @ 1 ms. select the zener or tvs clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded. ncp1015 http://onsemi.com 18 typical application examples a 6.5 w ncp1015 ? based flyback converter. (for evaluation a universal ncp1012 demo ? board can be used) figure 27 shows a converter originally built with a ncp1012 which can be easily used for evaluation of ncp1015 device delivering 6.5 w from a universal volts input range. the board uses the dynamic self ? supply and a simplified zener ? type feedback. this configuration was selected for cost reasons and a more precise circuitry can be used, e.g. based on a tl431: figure 27. a ncp1012 ? based flyback converter delivering 6.5 w 1 2 j1 cee7.5/2 d1 d2 e1 10 /400 v e2 10 /63 v 2 3 7 2 1 gnd gnd gnd v cc drain fb gnd ic1 ncp1012 r2 150 k d5 u160 5 4 4 8 c2 2n2/y 4 8 7 6 5 tr1 1 e3 470 /25 v d6 b150 r3 100 r r4 180 r 2 1 zd1 11 v j2 czm5/2 ic2 pc817 c1 2n2/y 1n4007 1n4007 r1 47 r d3 d4 1n4007 1n4007 the converter built according to figure 28 layouts, gave the following results: ? efficiency at v in = 100 vac and p out = 6.5 w = 75.7% ? efficiency at v in = 230 vac and p out = 6.5 w = 76.5% figure 28. the ncp1012 ? based pcb layout and its associated component placement ncp1015 http://onsemi.com 19 a 7.0 w ncp1015 ? based flyback converter featuring low standby power figure 29 shows another typical application showing a ncp1015 ? 65 khz operating in a 7 w converter up to 70 c of ambient temperature. we can grow ? up the output power since an auxiliary winding is used, the dss is disabled, and thus offering more room for the mosfet. in this application, the feedback is made via a tlv431 whose low bias current (100 a min) helps to lower the no ? load standby power. 1 8 2 3 4 7 5 v cc nc nc fb gnd drain vbulk c2 47 f/ 450 v + 1n4148 d4 r2 3.3 k + c10 33 f/25 v r4 22 ncp1015 + 100 f/10 v c3 c9 1 nf c8 10 nf 400 v r7 100 k/ 1 w d3 mur160 t1 12 v @ 0.5 a gnd d2 mbrs360t3 + + 100 f/16 v c7 + c6 c8 470 f/16 v r5 39 k r3 1 k ic1 sfh6156 ? 2 c4 100 nf ic2 tlv431 r6 4.3 k c5 2.2 nf y1 type t1 aux l2 22 h nc figure 29. a typical converter delivering 5 w from a universal mains measurements have been taken from a demonstration board implementing figure 12 12?s sketch and the following results were achieved, with either the auxiliary winding in place or through the dynamic self ? supply: v in = 230 vac, auxiliary winding, p out = 0, p in = 60 mw v in = 100 vac, auxiliary winding, p out = 0, p in = 42 mw v in = 230 vac, dynamic self ? supply, p out = 0, p in = 300 mw v in = 100 vac, dynamic self ? supply, p out = 0, p in = 130 mw p out = 7 w, = 81% @ 230 vac, with aux winding p out = 7 w, = 81.3% @ 100 vac, with aux winding for a quick evaluation of figure 29 application example, the following transformers are available from coilcraft: a9619 ? c, l p = 3 mh, np : ns = 1: 0.1, 7 w application on universal mains, including auxiliary winding, ncp1015 ? 65 khz a0032 ? a, l p = 6 mh, np : ns = 1: 0.055, 10 w application on european mains, dss operation only, ncp1015 ? 65 khz coilcraft 1102 silver lake road cary, il 60013 email: info@coilcraft.com tel. : 847 ? 639 ? 6400 fax.: 847 ? 639 ? 1469 ncp1015 http://onsemi.com 20 ordering information device order number frequency (khz) package type shipping ? r dson ( ) ipk (ma) ncp1015ap065g 65 pdip ? 7 (pb ? free) 50 units / rail 11 450 ncp1015ap100g 100 pdip ? 7 (pb ? free) 11 450 ncp1015st65t3g 65 sot ? 223 (pb ? free) 4000 / tape & reel 11 450 NCP1015ST100T3G 100 sot ? 223 (pb ? free) 11 450 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncp1015 http://onsemi.com 21 package dimensions pdip ? 7 ap suffix case 626a ? 01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. package contour optional (round or square corners). 4. dimension l to center of lead when formed parallel. 5. dimensions a and b are datums. 14 5 8 f note 3 ? t ? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 b a ncp1015 http://onsemi.com 22 package dimensions sot ? 223 st suffix case 318e ? 04 issue l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 a1 b1 d e b e e1 4 123 0.08 (0003) a l1 c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. h e dim a min nom max min millimeters 1.50 1.63 1.75 0.060 inches a1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 d 6.30 6.50 6.70 0.249 e 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 nom max l1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 h e ? ? e1 0 1 0 0 1 0 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp1015/d sensefet is a trademark of semiconductor components industries, llc (scillc). publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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